{
  "generated": "2026-10-18T16:09:06+0800",
  "count": 6,
  "publications": [
    {
      "id": "liu2027rapid",
      "type": "inproceedings",
      "title": "RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay",
      "authors": ["Haichuan Liu", "Zizheng Guo", "Zuodong Zhang", "Yuanqing Cheng", "Guannan Guo", "Runsheng Wang", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan, 2027.",
      "venue_short": "ASPDAC'27",
      "venue_url": "https://www.aspdac.com/aspdac2027/",
      "date": "2027-01-25",
      "year": "2027",
      "url": "https://lhaic.top/publication/2027-01-25-rapid",
      "pdf": "https://lhaic.top/files/ASPDAC2027_RAPID.pdf",
      "doi": "10.1145/3840404.3848149",
      "arxiv": null,
      "abstract": "Iterative physical-design optimization requires accurate timing feedback at proxy-timer speed. Conventional interconnect models expose an accuracy–efficiency tradeoff: Elmore delay is fast but loses waveform-shape information, whereas higher-order methods improve fidelity at the cost of more expensive distribution or waveform evaluation. We introduce RAPID, a ratio-based analytical proxy that moves Elmore delay toward higher-order timing fidelity through a positive, slew-aware delay-ratio correction. RAPID derives the correction from Wilson–Hilferty asymptotics of a moment-matched Gamma response and extends it to finite input transitions through normalized-slew dilution. The resulting ratio is computed by an Elmore-isomorphic linear-time traversal and used to calibrate interconnect delay and slew within a nonlinear delay model (NLDM)-compatible effective-load flow. On TAU benchmarks, RAPID achieves average R² = 0.9905 and end-to-end report_timing speedups of 9.84× over PrimeTime and 32.70× over OpenSTA. Without retuning, it reaches average R² = 0.9949 and mean absolute error (MAE) = 0.526 ps on unseen industrial ARM designs at Elmore-level runtime. In the evaluated repair flow, RAPID improves sign-off worst negative slack (WNS) and total negative slack (TNS) by up to 22.28% and 15.44%, respectively.",
      "bibtex": "@inproceedings{liu2027rapid,\n  title     = { RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay },\n  author    = { Haichuan Liu and Zizheng Guo and Zuodong Zhang and Yuanqing Cheng and Guannan Guo and Runsheng Wang and Yibo Lin },\n  booktitle = { IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) },\n  year      = { 2027 },\n  doi       = { 10.1145/3840404.3848149 },\n  url       = { https://doi.org/10.1145/3840404.3848149 },\n}"
    },
    {
      "id": "liu2027pact",
      "type": "inproceedings",
      "title": "PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs",
      "authors": ["Haichuan Liu", "Zizheng Guo", "Zuodong Zhang", "Haoyi Zhang", "Chunyuan Zhao", "Kairong Guo", "Shenglu Hua", "Guannan Guo", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan, 2027.",
      "venue_short": "ASPDAC'27",
      "venue_url": "https://www.aspdac.com/aspdac2027/",
      "date": "2027-01-25",
      "year": "2027",
      "url": "https://lhaic.top/publication/2027-01-25-pact",
      "pdf": "https://lhaic.top/files/ASPDAC2027_PACT.pdf",
      "doi": "10.1145/3840404.3848150",
      "arxiv": null,
      "abstract": "Timing ECO flows repeatedly modify circuit topology, yet GPU-accelerated Static Timing Analysis (STA) engines built on static sparse layouts commonly rebuild and resynchronize the GPU-visible topology after each edit. Existing GPU-accelerated STA work instead co-designs dynamic representations with application-specific kernels, exposing representation assumptions to consumers and limiting reuse with CSR-based analyses. We present PACT (Private Atomic Committed Topology), a runtime contract that keeps the mutation representation runtime-private behind a representation-independent committed-traversal contract. GPU traversal consumers observe only a committed CSR-compatible view. PACT maintains this view through a contract-preserving localized commit realization that maps objects created by or incident to each edit batch into affected CSR rows, rematerializes each complete affected CSR row, and exposes the new view after synchronization. Dependency-ordered contract composition applies the same contract to explicit netlist/parasitic edits and timing-state edits derived from their committed frontiers. The selected realization achieves 3.59× the geometric-mean topology-maintenance throughput of a reimplemented Dual-CSR baseline. In an in-house CPU–GPU STA engine, PACT delivers 2.72× and 2.96× end-to-end speedups over full rebuild under two ECO schedules with identical complete timing outputs. Scalability studies further delimit its measured operating range across host thread counts and update-batch sizes.",
      "bibtex": "@inproceedings{liu2027pact,\n  title     = { PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs },\n  author    = { Haichuan Liu and Zizheng Guo and Zuodong Zhang and Haoyi Zhang and Chunyuan Zhao and Kairong Guo and Shenglu Hua and Guannan Guo and Yibo Lin },\n  booktitle = { IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) },\n  year      = { 2027 },\n  doi       = { 10.1145/3840404.3848150 },\n  url       = { https://doi.org/10.1145/3840404.3848150 },\n}"
    },
    {
      "id": "guo2026scoutcell",
      "type": "inproceedings",
      "title": "ScoutCell: Sensitivity-Guided Coupling Optimization for Timing-Driven Standard Cell Synthesis",
      "authors": ["Kairong Guo", "Haoyi Zhang", "Haichuan Liu", "Chunyuan Zhao", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov, 2026.",
      "venue_short": "ICCAD'26",
      "venue_url": "https://iccad.com/2026",
      "date": "2026-11-08",
      "year": "2026",
      "url": "https://lhaic.top/publication/2026-11-08-scoutcell",
      "pdf": "https://lhaic.top/files/ICCAD2026_ScoutCell.pdf",
      "doi": "10.1145/3831252.3834054",
      "arxiv": null,
      "abstract": "In advanced-node standard cell synthesis, timing optimization is increasingly limited by parasitic coupling effects that are not well captured by wirelength-centric heuristics alone. While recent timing-driven approaches improve delay by shortening critical paths, they often overlook the disproportionate impact of parasitic coupling on specific delay-critical net pairs. In this work, we propose ScoutCell, a sensitivity-guided standard-cell synthesis framework that follows a characterize-then-optimize flow. ScoutCell first extracts a reusable pairwise sensitivity prior from an anchor layout, and then uses this prior to guide coupling-aware placement candidate screening and routing refinement toward isolating delay-critical net-pair interactions. Experiments on the ASAP7 predictive process design kit show that ScoutCell consistently outperforms both the area/wirelength-driven baseline and a state-of-the-art timing-driven cell synthesis method, reducing the average cell delay by 0.6%/1.2% and 0.2%/0.5% on combinational/sequential cells, respectively. Under a full logic-synthesis and physical-implementation flow, ScoutCell further improves the average post-route achievable frequency by 8.5% and 4.7% over the two baselines, demonstrating that its cell-level timing benefits remain visible at the design level.",
      "bibtex": "@inproceedings{guo2026scoutcell,\n  title     = { ScoutCell: Sensitivity-Guided Coupling Optimization for Timing-Driven Standard Cell Synthesis },\n  author    = { Kairong Guo and Haoyi Zhang and Haichuan Liu and Chunyuan Zhao and Yibo Lin },\n  booktitle = { IEEE/ACM International Conference on Computer-Aided Design (ICCAD) },\n  year      = { 2026 },\n  doi       = { 10.1145/3831252.3834054 },\n  url       = { https://doi.org/10.1145/3831252.3834054 },\n}"
    },
    {
      "id": "liu2026elmoreceff",
      "type": "inproceedings",
      "title": "ElmoreCeff: A GPU-Friendly Elmore-Like Delay Calculator with a Closed-Form Effective Capacitance Model",
      "authors": ["Haichuan Liu", "Zizheng Guo", "Runsheng Wang", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM International Symposium of EDA (ISEDA), Singapore, May, 2026.",
      "venue_short": "ISEDA'26",
      "venue_url": "https://www.eda2.com/iseda/index.html",
      "date": "2026-05-08",
      "year": "2026",
      "url": "https://lhaic.top/publication/2026-05-08-elmoreceff",
      "pdf": "https://lhaic.top/files/ISEDA2026_ElmoreCeff.pdf",
      "doi": null,
      "arxiv": null,
      "abstract": "Accurate and efficient delay calculation is critical for timing-driven optimization, yet existing methods require a trade-off between fast but inaccurate Elmore timers and accurate but slow model order reduction (MOR) techniques. To bridge this gap, we introduce ElmoreCeff, a GPU-friendly Elmore-like delay calculator based on a closed-form effective capacitance model. ElmoreCeff can achieve speedups of up to 40.95\\(\\times\\) and 5.95\\(\\times\\) over CPU- and GPU-based MOR timers, respectively, while achieving comparable accuracy. This advantage enhances final quality of results (QoR) of timing optimization, improving worst negative slack (WNS) and total negative slack (TNS) by up to 8.4% and 5.4% compared to optimizations guided by the standard Elmore timer.",
      "bibtex": "@inproceedings{liu2026elmoreceff,\n  title     = { ElmoreCeff: A GPU-Friendly Elmore-Like Delay Calculator with a Closed-Form Effective Capacitance Model },\n  author    = { Haichuan Liu and Zizheng Guo and Runsheng Wang and Yibo Lin },\n  booktitle = { IEEE/ACM International Symposium of EDA (ISEDA) },\n  year      = { 2026 },\n}"
    },
    {
      "id": "guo2026heterosta",
      "type": "inproceedings",
      "title": "HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support",
      "authors": ["Zizheng Guo", "Haichuan Liu", "Xizhe Shi", "Shenglu Hua", "Zuodong Zhang", "Chunyuan Zhao", "Runsheng Wang", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Hong Kong, Jan, 2026.",
      "venue_short": "ASPDAC'26",
      "venue_url": "https://www.aspdac.com/aspdac2026/index.html",
      "date": "2026-01-19",
      "year": "2026",
      "url": "https://lhaic.top/publication/2026-01-19-heterosta",
      "pdf": "https://arxiv.org/pdf/2511.11660v1",
      "doi": "10.1109/ASP-DAC66049.2026.11420338",
      "arxiv": "2511.11660",
      "abstract": "We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile accuracy-speed choices without relying on an external golden tool, (2) robust support for industry formats, including especially the .sdc constraints containing all common timing exceptions, clock domains, and case analysis modes, and (3) end-to-end GPU-acceleration for both graph-based and path-based timing queries, all exposed as a zero-overhead flattened heterogeneous application programming interface (API). HeteroSTA is publicly available with both a standalone binary executable and an embeddable shared library targeting ubiquitous academic and industry applications. Example use cases as a standalone tool, a timing-driven DREAMPlace 4.0 integration, and a timing-driven global routing integration have all demonstrated remarkable runtime speed-up and comparable quality.",
      "bibtex": "@inproceedings{guo2026heterosta,\n  title     = { HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support },\n  author    = { Zizheng Guo and Haichuan Liu and Xizhe Shi and Shenglu Hua and Zuodong Zhang and Chunyuan Zhao and Runsheng Wang and Yibo Lin },\n  booktitle = { IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) },\n  year      = { 2026 },\n  doi       = { 10.1109/ASP-DAC66049.2026.11420338 },\n  url       = { https://doi.org/10.1109/ASP-DAC66049.2026.11420338 },\n}"
    },
    {
      "id": "liu2025incregpusta",
      "type": "inproceedings",
      "title": "IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows",
      "authors": ["Haichuan Liu", "Zizheng Guo", "Runsheng Wang", "Yibo Lin"],
      "category": "conferences",
      "venue": "IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct, 2025.",
      "venue_short": "ICCAD'25",
      "venue_url": "https://2025.iccad.com/",
      "date": "2025-10-26",
      "year": "2025",
      "url": "https://lhaic.top/publication/2025-10-26-incregpusta",
      "pdf": "https://lhaic.top/files/ICCAD2025_IncreGPUSTA.pdf",
      "doi": "10.1109/ICCAD66269.2025.11240636",
      "arxiv": null,
      "abstract": "Static timing analysis (STA) plays an essential role in VLSI design optimization. While CPU-based incremental STA methods reduce computational overhead by selectively updating affected circuit regions, and GPU-accelerated engines improve full-circuit analysis throughput, effectively combining these approaches has remained challenging. Existing solutions offer only partial incrementality, either switching to CPU processing for small modifications or handling solely delay value changes without supporting structural updates. We introduce IncreGPUSTA, a novel GPU-accelerated incremental STA algorithm with dual-CSR data structures and incremental levelization that efficiently processes timing updates for both localized and structural modifications. Experimental results on industrial benchmarks demonstrate speedups of up to 3.06\\(\\times\\) over GPU full Timer and up to 72.50\\(\\times\\) over CPU incremental Timer for million-scale designs.",
      "bibtex": "@inproceedings{liu2025incregpusta,\n  title     = { IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows },\n  author    = { Haichuan Liu and Zizheng Guo and Runsheng Wang and Yibo Lin },\n  booktitle = { IEEE/ACM International Conference on Computer-Aided Design (ICCAD) },\n  year      = { 2025 },\n  doi       = { 10.1109/ICCAD66269.2025.11240636 },\n  url       = { https://doi.org/10.1109/ICCAD66269.2025.11240636 },\n}"
    }
  ]
}